The present invention generally relates to a system for automating logical designing of LSIs and the like. More particularly, the present invention is concerned with a logic generating system suited for profitably automating the designing of logic circuits in which many a register-transfer logic is adopted, as in the case of LSIs adapted to operate with microprograms.
Heretofore, automatic generation of the logic circuits has been attempted mainly with the aid of design specifications described in terms of truth tables or logical expressions. On the other hand, in the process of manual logic design of LSIs as practiced, the job of designing a logic circuit in detail on the basis of a truth table and/or logical expressions has been done only in conjunction with small scale discrete circuitries. In practice, most specifications are described at a register-transfer level corresponding to a high abstraction level. In the field of the related art, however, no approach has been proposed concerning the generation of detailed logic design directly from the descriptions in such a register-transfer level specification.
As the related art, there are the techniques disclosed in "LSS, A system For Production Logic Synthesis"; IBM J. RES. Develop. Vol. 28, No. 5, (Sep., 1984), pp. 537-545, "Optimization of Combination Logic Using a Rule Based Expert System"; Journal of I.E.E.E. Design and Test, (Aug., 1985), pp. 22-32, and "Logic Synthesis System"; Information Processing Society of Japan, Research Materials For Design-Automatization, No. 34-2, (Dec., 1980).
The systems of the related art mentioned above lack the capability of analyzing the contents of the specification described at the register-transfer level of high abstraction for directly or straightforwardly generating the logic desired by the designer from such a specification. Consequently, the input specifications must beforehand be rewritten in terms of truth tables or logical expressions. This can give rise to a problem. When rewritten in terms of truth tables, the specifications are expressed as input/output relations, which means that the meaningful information of the "data transfer" becomes less definite. As a result of this, difficulty is naturally encountered in the automatic logic generation with respect to the realization of quality that is comparable to that of the manual design in which consideration can fully be paid as to the optimization. This is another problem. Besides, rewriting of the specifications in terms of the logical expressions requires a lot of time and labour almost as much as the detailed logic design so that the phrase "automatic logic generation" might be considered a misnomer